1. Field of the Invention
The present invention relates to a design system of a functional circuit. In addition, the present invention relates to a method for designing a functional circuit. The present application claims priority under 35 USC §119 to Japanese application serial no. 2008-247509 filed Sep. 26, 2008 in Japan.
2. Description of the Related Art
In recent years, research and development of semiconductor devices in which transistors formed using polycrystalline semiconductors or the like are used for switching elements of pixel portions or driver circuits of pixels have been actively conducted.
Further, semiconductor devices in which display elements and functional circuits which are formed using the transistors are formed over the same substrate have been researched and developed. As the functional circuits, for example, CPUs, image processing circuits, memories, or the like can be given. In order to enhance added value of the semiconductor device, for example, improvement in processing capability, reduction in area, and decrease in power consumption, or the like is required for the functional circuit.
Focusing on the efficiency of design, functional circuits are generally designed by synchronous design. In synchronous design in recent years, circuits are represented with a hardware description language of register transfer level which conforms to IEEE standards, a net list which indicates a functional circuit is generated with a use of a logic synthesizer, and a layout is designed based on the generated net list with a use of an automatic placement and routing tool while an operation timing is considered. A functional circuit manufactured by such a design method is a synchronous circuit in which each unit circuit inside the functional circuit operates by synchronizing with a clock signal. Note that a description in a hardware language at the register transfer level is also referred to as an RTL description in this document.
On the other hand, a functional circuit in which each unit circuit inside does not operate by synchronizing with a clock signal is referred to as an asynchronous circuit.
The synchronous circuit is characterized by high efficiency of design and a large circuit scale or high power consumption as compared to the asynchronous circuit. On the other hand, the asynchronous circuit is characterized by low efficiency of design, accumulation of delays, and a small circuit scale or low power consumption. Accordingly, a functional circuit which has an advantage of the asynchronous circuit by making part of the functional circuit asynchronous while an advantage of the synchronous circuit is maintained (hereinafter such a functional circuit is referred to as an asynchronous substitutional functional circuit), and design of such a functional circuit are desired.
In the case where a functional circuit to be designed is the above-described asynchronous substitutional functional circuit, the functional circuit has been designed by a design method in which an asynchronous unit circuit is manually substituted for a synchronous unit circuit (such a design method is also referred to as a hand design). However, circuit design by the above-described hand design has a problem in that the efficiency of design and reliability are low. As a method for solving the problem, the following is suggested: a design aid device which extracts a description which indicates a certain unit circuit (e.g., a description which indicates a binary counter circuit) from an RTL description which represents circuits and automatically substitutes a corresponding description which indicates an asynchronous circuit (e.g., a description which indicates an asynchronous binary counter circuit) for the extracted description (for example, Patent Document 1).
[Reference]
[Patent Document ]
    [Patent Document 1] Japanese Published Patent Application No. H9-231259
However, with a conventional design method including that disclosed in Patent Document 1, delays are accumulated in the asynchronous circuit. Therefore, if a description indicating an asynchronous circuit is substituted for a description indicating a synchronous circuit, it is difficult to pass timing verification in designing a layout in some cases. Note that to “pass” above means that the result of the timing verification in designing the layout is correct.
Here, the conventional design method of an asynchronous substitutional functional circuit will be described in detail with reference to FIG. 14 and FIG. 15.
FIG. 14 is a flow chart of synchronous circuit design. As shown in FIG. 14, in the conventional synchronous circuit design, logic is synthesized by using an RTL description which represents a circuit as a first step (s1 in FIG. 14); then, placement and routing is performed as a second step (s2 in FIG. 14); timing verification is performed as a third step (s3 in FIG. 14); and the design is completed in the case of passing the timing verification in a fourth step (s4 in FIG. 14). Note that the placement and routing in the second step and the timing verification in the third step are collectively referred to as layout design. In addition, the completion of the design means a state in which masks can be ordered. Further, in the case where the timing verification cannot be passed, the flow goes back to a stage of generating an RD, description as a fifth step (s5 in FIG. 14) to perform appropriate correction. This flow is the conventional synchronous circuit design.
On the other hand, FIG. 15 is a flow chart of the design of the asynchronous substitutional functional circuit disclosed in Patent Document 1. As shown in FIG. 15, in the design of the asynchronous substitutional functional circuit disclosed in Patent Document 1, as a first step (s0 in FIG. 15), an RTL description which represents an asynchronous substitutional functional circuit is generated by extracting a description which indicates a certain unit circuit (a description which indicates a synchronous binary counter circuit) from an RTL description which represents circuits and automatically substituting a description of a corresponding asynchronous circuit (a description which indicates an asynchronous binary counter circuit) for the extracted description of the certain unit circuit. After that, like the flow chart in FIG. 14, logic is synthesized by using the generated RTL description that represents the asynchronous substitutional functional circuit as a second step (s1 in FIG. 15); placement and routing is performed as a third step (s2 in FIG. 15); a layout is designed by timing verification as a fourth step (s3 in FIG. 15); and the design is completed in the case of passing the timing verification in a fifth step (s4 in FIG. 15). Further, in the case where the verification of the timing cannot be passed, the flow goes back to a stage of generating an RTL description as a sixth step (s5 in FIG. 15) to perform appropriate correction. This flow is the design of the asynchronous substitutional functional circuit disclosed in Patent Document 1.
As described above, in designing the asynchronous substitutional functional circuit, as compared to the original RTL description, there is a high possibility that the RTL description generated by the substitution process cannot pass the timing verification in designing the layout due to accumulation of delays in the asynchronous circuit. However, depending on characteristics of a device or a circuit configuration, the timing verification in designing the layout is passed in some cases even when delays are accumulated. Therefore, whether the timing verification is passed or not cannot be determined at the time of synthesizing logic. In other words, a possibility that the flow goes back to a stage of generating an RTL description to perform appropriate correction after the design step proceeds up to layout design is higher than that of the conventional synchronous circuit design, which leads to a problem of waste of time. There is concern that the waste of time for design may indirectly cause decrease in efficiency of design and increase in a circuit scale or power consumption depending on demand for design from market forces and the like.